1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to such a device having a semiconductor chip which is covered with a sealing resin. The present invention may also relate to a method of manufacturing such a device.
2. Background
In recent years, the miniaturization of portable devices has led to a demand for a reduction in the size and thickness of semiconductor devices incorporated in the portable devices. For example, a BGA (Ball Grid Array) type semiconductor device has become less rigid as its wiring substrate and semiconductor chips get thinner and thinner. As a result, a warpage of the semiconductor device caused by the effect of a sealing resin has grown into a serious problem.
In general, the BGA type semiconductor device is sealed with a filler-containing resin in the following manner. A wiring substrate having multiple product regions is clamped with a molding die, and a melted sealing resin is so injected into a cavity of the molding die by a transfer molding method that the sealing resin proceeds from the gate side to the air-vent side to form a sealing resin layer covering the whole of multiple product regions.
Japanese Laid-Open Patent Publication No. 2011-228603 discloses a configuration in which a semiconductor chip is bonded to a wiring substrate such that the semiconductor chip is located offset to the center of the wiring substrate and closer to the air-vent side and is sealed with a filler-containing resin.
An analysis made by the inventor of the present invention has led to the following analytical results.
A sealing resin layer sealing a semiconductor chip usually contains a filler. As a result, when the sealing resin layer is formed by the transfer molding method, a difference in content ratio of the filler to the resin (filler content ratio) is created between the gate side, to which the sealing resin is supplied, and the air-vent side, from which air is discharged, in the sealing resin layer. Specifically, in the sealing resin layer, the air-vent side of the sealing resin becomes larger in filler content ratio than the gate side of the sealing resin.
A linear expansion coefficient distribution in the sealing resin layer changes depending on a filler content ratio distribution in the sealing resin layer. Specifically, in the sealing resin layer, the filler content is smaller than the resin content on the gate side where the resin volume turns out to be greater and therefore a linear expansion coefficient becomes larger, while the filler content is larger than the resin content on the air-vent side where the resin volume turns out to be smaller and therefore a linear expansion coefficient becomes smaller. Such a difference in linear expansion coefficient leads to a phenomenon that the semiconductor device and the wiring substrate warp inward on the gate side and outward on the air-vent side. As a result, the semiconductor device may become inferior in mountability.
Japanese Laid-Open Patent Publication No. 2011-228603 discloses the configuration in which the semiconductor chip is mounted and sealed in the offset location closer to the air-vent side on the wiring substrate. By mounting the semiconductor chip in the offset location closer to the air-vent side where the filler content ratio is high in this manner, the resin volume on the gate side is increased as the same on the air-vent side is decreased in the sealing resin layer. This leads to a growing warpage of the semiconductor device.